1. Field of the Invention
This invention relates to the manufacture of a dynamic random access memory (DRAM) device and more particularly, to a method for fabricating an array of DRAM cells, each DRAM cell having a stacked capacitor.
2. Description of the Related Art
Dynamic random access memory (DRAM) circuits are used in the electronics industry for storing information as binary data DRAMs are formed on chips diced from semiconductor substrates and consist of an array of memory cells and peripheral circuits for randomly accessing the memory cells to store and retrieve digital information. Individual DRAM cells are composed of a single field effect transistor (FET), commonly referred to as a pass transistor, and a charge storage capacitor. Some storage capacitors in modem DRAMs are formed within trenches in the semiconductor substrate (i.e., trench capacitors), or alternatively, storage capacitors may be formed as stacked capacitors with the conductive plates of the stacked capacitors extending over the pass transistor and over other portions of the DRAM cell.
In recent years, the density of cells on the DRAM chip has increased dramatically because of improvements in such semiconductor technologies as high resolution photolithography and directional plasma etching. Recent DRAM designs provide 64 Megabits of storage on a single chip, and the number of bits on a chip is expected to reach 256 Mbits by the year 1998. As this cell density increases, it is necessary to reduce the area of each cell to maintain a reasonable chip size and to improve the circuit performance. Unfortunately, as the cell size decreases it is necessary to reduce the storage capacitor size to limit the amount of substrate surface area occupied by the capacitor. This results in decreased charge stored on the capacitor that makes it more difficult to detect the stored charge on the capacitor during the read cycle because of the lower signal to noise ratio at the sense amplifiers. These smaller charge storage cells also require more frequent refresh cycles to maintain measurable charge levels on the capacitors. Therefore, there is a strong need in the electronics industry to increase the capacitance that is obtained from a charge storage capacitor while reducing the cell area.
The stacked capacitor approach to increasing capacitance has received considerable interest in recent years because of the variety of ways that the capacitor electrodes can be formed in the vertical (third) dimension over the FET and within the cell area to increase the capacitance while maintaining or reducing the cell area. For example, U.S. Pat. No. 5,362,664 to Jun describes a method for forming a stacked capacitor having fin-shaped electrodes. The Jun patent is exemplary of at least some conventional stacked capacitor formation processes.
Another approach for increasing the memory cell capacitance is to fabricate both a trench capacitor and a stacked capacitor in the same DRAM cell area. For example, U.S. Pat. No. 5,234,856 to Gonzales describes a method for forming a trench capacitor. The method involves etching a trench in the node contact area (one of the two FET source/drain areas) of the substrate, and then forming a conventional single plate storage-node electrode (bottom electrode) for the stacked capacitor that also serves as the bottom electrode for the trench capacitor. This results in a stacked-trench capacitor that increases the cell capacitance and also makes the memory cell more immune to soft errors (discharging) induced by high energy particles, such as naturally occurring alpha particles.
However, as the DRAM cell area continues to decrease in size, there is still a strong need in the semiconductor industry to maintain or further increase the capacitance of the storage capacitor while providing a low cost manufacturing process.